Input your RISC-V code here:
Memory Address | Decimal | Hex | Binary |
---|---|---|---|
0x00000000 | 0 | 0x00000000 | 0b00000000000000000000000000000000 |
0x00000004 | 0 | 0x00000000 | 0b00000000000000000000000000000000 |
0x00000008 | 0 | 0x00000000 | 0b00000000000000000000000000000000 |
0x0000000c | 0 | 0x00000000 | 0b00000000000000000000000000000000 |
0x00000010 | 0 | 0x00000000 | 0b00000000000000000000000000000000 |
0x00000014 | 0 | 0x00000000 | 0b00000000000000000000000000000000 |
0x00000018 | 0 | 0x00000000 | 0b00000000000000000000000000000000 |
0x0000001c | 0 | 0x00000000 | 0b00000000000000000000000000000000 |
0x00000020 | 0 | 0x00000000 | 0b00000000000000000000000000000000 |
0x00000024 | 0 | 0x00000000 | 0b00000000000000000000000000000000 |
Init Value | Register | Decimal | Hex | Binary |
---|---|---|---|---|
0 | x0 (zero) | 0 | 0x00000000 | 0b00000000000000000000000000000000 |
x1 (ra) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x2 (sp) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x3 (gp) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x4 (tp) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x5 (t0) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x6 (t1) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x7 (t2) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x8 (s0/fp) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x9 (s1) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x10 (a0) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x11 (a1) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x12 (a2) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x13 (a3) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x14 (a4) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x15 (a5) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x16 (a6) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x17 (a7) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x18 (s2) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x19 (s3) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x20 (s4) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x21 (s5) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x22 (s6) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x23 (s7) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x24 (s8) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x25 (s9) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x26 (s10) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x27 (s11) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x28 (t3) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x29 (t4) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x30 (t5) | 0 | 0x00000000 | 0b00000000000000000000000000000000 | |
x31 (t6) | 0 | 0x00000000 | 0b00000000000000000000000000000000 |
Instr Type | Instr | Struct | Operation | Function | Type |
---|---|---|---|---|---|
Arithmetics | add | add rd, rs1, rs2 | rd = rs1 + rs2 | Addition | R-Type |
Arithmetics | addi | addi rd, rs1, imm | rd = rs1 + SignExt(imm) | Addition Immediate | I-Type |
Arithmetics | sub | sub rd, rs1, rs2 | rd = rs1 - rs2 | Substraction | R-Type |
Logical | and | and rd, rs1, rs2 | rd = rs1 & rs2 | AND | R-Type |
Logical | andi | andi rd, rs1, imm | rd = rs1 & SignExt(imm) | AND Immediate | R-Type |
Logical | or | or rd, rs1, rs2 | rd = rs1 | rs2 | OR | R-Type |
Logical | ori | ori rd, rs1, imm | rd = rs1 | SignExt(imm) | OR Immediate | I-Type |
Logical | xor | xor rd, rs1, rs2 | rd = rs1 ^ rs2 | XOR | R-Type |
Logical | xori | xori rd, rs1, imm | rd = rs1 ^ SignExt(imm) | XOR Immediate | I-Type |
Sets | slt | slt rd, rs1, rs2 | rd = (rs1 < rs2) ? 1:0 | Set If Less Then | R-Type |
Sets | slti | slti rd, rs1, imm | rd = (rs1 < SignExt(imm)) ? 1:0 | Set If Less Then Immediate | I-Type |
Sets | sltu | sltu rd, rs1, rs2 | rd = (rs1 < rs2) ? 1:0 | Set If Less Then Unsigned | R-Type |
Sets | sltiu | sltiu rd, rs1, imm | rd = (rs1 < SignExt(imm)) ? 1:0 | Set If Less Then Immediate Unsigned | I-Type |
Shifts | sra | sra rd, rs1, rs2 | rd = rs1 >>> rs2 | Shift Right Arithmetic | R-Type |
Shifts | srai | srai rd, rs1, imm | rd = rs1 >>> uimm | Shift Right Arithmetic Immediate | I-Type |
Shifts | srl | srl rd, rs1, rs2 | rd = rs1 >> rs2 | Shift Right Logical | R-Type |
Shifts | srli | srli rd, rs1, imm | rd = rs1 >> uimm | Shift Right Logical Immediate | I-Type |
Shifts | sll | sll rd, rs1, rs2 | rd = rs1 << rs2[4:0] | Shift Left Logical | R-Type |
Shifts | slli | slli rd, rs1, imm | rd = rs1 << uimm | Shift Left Logical Immediate | I-Type |
Memory | lw | lw rd, imm(rs1) | rd = Memory[(rs1 + imm)[31:0]] | Load Word | I-Type |
Memory | sw | sw rs2, imm(rs1) | Memory[(rs1 + imm)[31:0]] = rs2 | Store Word | S-Type |
Memory | lb | lb rd, imm(rs1) | rd = Memory[SignExt(rs1 + imm)][7:0] | Load Byte | I-Type |
Memory | lbu | lb rd, imm(rs1) | rd = Memory[rs1 + imm][7:0] | Load Byte (unsigned) | I-Type |
Memory | lh | lh rd, imm(rs1) | rd = Memory[SignExt(rs1 + imm)][15:0] | Load LWord | I-Type |
Memory | lhu | lhu rd, imm(rs1) | rd = Memory[(rs1 + imm)][15:0] | Load LWord (unsigned) | I-Type |
Memory | sb | sb rs2, imm(rs1) | Memory[(rs1 + imm)][15:0] = rs2[15:0] | Store Byte | S-Type |
PC | lui | lui rd, imm | rd = [upimm,0x000] | Load Upper Immediate | U-Type |
PC | auipc | auipc rd, imm | rd = [upimm, 0x000] + PC | Add Upper Immediate to PC | U-Type |
Jumps | jal | jal rd, label | PC = label, rd = x0 = ra = PC + 4 | Jump And Link, imm is shifted << 1 | J-Type |
Jumps | jalr | jalr rd, rs1, imm | PC = rs1 + SignExt(imm), rd = PC + 4 | Jump And Link Register | I-Type |
Branches | beq | beq rs1, rs2, label | if(rs1 == rs2) PC = label | Branch If Equal | B-Type |
Branches | bne | bne rs1, rs2, label | if(rs1 != rs2) PC = label | Branch if Not Equal | B-Type |
Branches | blt | blt rs1, rs2, label | if(rs1 < rs2) PC = label | Branch If Less Then | B-Type |
Branches | bge | bge rs1, rs2, label | if(rs1 >= rs2) PC = label | Branch If Greater Than Or Equal | B-Type |
Branches | bltu | bltu rs1, rs2, label | if(rs1 < rs2) PC = label | Branch If Less Then Unsigned | B-Type |
Branches | bgeu | bgeu rs1, rs2, label | if(rs1 >= rs2) PC = label | Branch If Greater Then Or Equal Unsigned | B-Type |
Register | ABI Name | Description/th> | Saver |
---|---|---|---|
x0 | zero | Hard-wired zero | - |
x1 | ra | Return Address | Caller |
x2 | sp | Stack Pointer | Callee |
x3 | gp | Global Pointer | - |
x4 | tp | Thread Pointer | - |
x5 | t0 | Temporary / alternate link register | Caller |
x6-x7 | t1-t2 | Temporaries | Caller |
x8 | s0/fp | Saved Register | Callee |
x9 | s1 | Saved register | Callee |
x10-x11 | a0-a1 | Function arguments/return values | Caller |
x12-x17 | a2-a7 | Function arguments | Caller |
x18-x27 | s2-s11 | Saved Registers | Callee |
x28-x31 | t3-t6 | Temporaries | Caller |
RISC-V Reference: riscv-spec-v2.2.pdf